Group

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  Jie Zhou

  PhD Student

  Jie is committed to exploring the application of LLMs in the realm of Hardware Description Languages (HDLs), with a focus on automating the generation and debugging processes.

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  Xiaomeng Han

  PhD Student

  Xiaomeng focuses on software/hardware co-design of LLMs. He is committed to the edge deployment of LLMs through software/hardware co-design, accelerating the application of LLMs in real-world scenarios.

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  Renshuang Jiang

  PhD Student co-supervised with Pan Dong @ NUDT

  Renshuang works on modular operating-system architecture, including flexible isolation and refactoring systems. She has previously worked on enhancing the safety of the Rust programming language and is also interested in using Rust to rewrite operating systems.

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  Ke Xu

  PhD Student co-supervised with Weiwei Shan @ SEU

  Ke is a PhD candidate in Electronic Science and Technology at Southeast University. His current research focuses on leveraging LLMs for RTL code debugging and multi-server simulation. GitHub.

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  Yuchen Hu

  PhD Student co-supervised with Weiwei Shan @ SEU

  Yuchen's research interests include the application of Large Language Models (LLMs) in hardware design verification. He focuses on integrating LLMs with the Universal Verification Methodology (UVM) to automate the testing and repair of error-prone RTL code, aiming to improve verification efficiency and overcome the limitations of existing methods.

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  Tinglue Wang

  PhD Student

  Tinglue completed his undergraduate studies at the School of Electronic Science and Engineering, SEU. He is interested in SoC/CPU architecture and digital circuit design, and is working on a safety-critical multi-core CPU architecture project based on the Berkeley Chipyard platform.

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  Zhenghui Zheng

  PhD Student

  Hui is interested in computer-architecture design, real-time operating systems, and computer theory such as scheduling, while also enjoying history, literature and philosophy.

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  Hui Wang

  PhD Student

  Hui's research interests centre on MLSys. He is dedicated to achieving efficient ML through the study of machine-learning algorithms and software/hardware infrastructure. GitHub.

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  Dean You

  PhD Student

  Dean's research interests centre on architectural techniques for: data prefetching for irregular memory-access patterns in hardware; run-time hardware support for processor security and reliability; and fine-grained pre-emptive techniques for NPUs.

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  Junhao Ye

  PhD Student

  Junhao's research interests center on LLM-aided RTL verification. He is currently working on UVM-based automation covering testbench and stimulus generation, as well as simulation feedback and refinement. He is also a content creator on social media. Homepage · Bilibili.

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  Jialin Sun

  PhD Student

  Jialin currently focuses on hardware/software co-simulation accelerators.

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  Jiapeng Guan

  PhD Student

  Jiapeng is committed to exploring LLM-based performance modelling for NPUs, drawing on his prior experience in NPU design and real-time systems.

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  Zhihang Tan

  Master's Student

  Zhihang focuses on hardware-based techniques for data prefetching to address memory latency in CPUs, particularly for irregular memory-access patterns in large-scale data processing. Future work may extend to using simulators for broader evaluation and optimisation.

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  Xiaoxuan Wang

  Master's Student

  Xiaoxuan focuses on hardware-based techniques for data prefetching, based on the execution order of instructions and the access patterns of data. Future work may extend to the architecture and optimisation of out-of-order processors.

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  Shiyue Zhang

  Master's Student

  Shiyue completed her undergraduate studies at the School of Electronic Science and Engineering, Southeast University. She is interested in the application of LLMs to circuits and digital circuit design, and is conducting research on the application of LLMs in circuits.

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  Jie Zhang

  Master's Student

  Jie's research interests centre on efficient AI systems, including NPU architecture, reliable AI accelerator design, and optimisation techniques for large language model inference.

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  Bing Guo

  Master's Student

  Bing's research interests include, but are not limited to, reliability, data prefetching, replacement algorithms and branch prediction. He focuses on developing efficient hardware techniques to improve processor performance and dependability.

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  Zhenyuan Wang

  Master's Student

  Zhenyuan focuses on processor design and optimisation, and is currently exploring data prefetching for irregular access patterns. His work aims to improve processor performance through advanced prefetching techniques and architectural optimisations.

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  Junyang Lu

  Master's Student

  Junyang is working on repository-level RTL code completion through iterative retrieval-augmented generation (RAG). This work aims to automate hardware design by leveraging cross-file context to improve generation accuracy. The research addresses semantic gaps through iterative retrieval, seeking to enhance the performance and reliability of large language models in complex RTL development.

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  Xinyao Jiao

  Master's Student

  Xinyao is working on repository-level RTL code generation based on multimodal retrieval-augmented generation (RAG), aiming to improve the automation and efficiency of hardware design. Her research combines code, specifications and simulation signals to improve the accuracy and reliability of RTL development.

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  Jiaming Suo

  Master's Student

  Jiaming focuses on the design of reliable and efficient quantisation accelerators. His research interests lie in hardware architectures and hardware/software co-design for improving the reliability of quantised neural-network computation, with an emphasis on low-overhead error-detection and protection mechanisms for AI accelerators.

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  Yongyuan Dai

  Master's Student

  Yongyuan focuses on NPU simulation and verification, with an emphasis on differential testing across different levels of abstraction. His current work explores efficient co-simulation and verification methodologies for NPU architectures.

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  Shiwen Gao

  Master's Student

  Shiwen is a Master's student at the School of Integrated Circuits, Southeast University. Her research focuses on leveraging LLMs for RTL code debugging.

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  Sen Wang

  Master's Student

  Sen's research interests include branch prediction and low-power processor design. His work aims to improve processor performance through advanced branch-prediction techniques and reduce energy consumption through low-power architectural techniques.

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  Hanyuan Liu

  Master's Student

  Hanyuan's research interests include automated SystemVerilog Assertion (SVA) generation, UVM testbench automation, and coverage-driven stimulus generation and refinement. Outside of his research, he enjoys anime and AI-assisted video creation.

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  Dingrong Pan

  Hardware Engineer · Part-time PhD Student

  Dingrong is a hardware verification engineer and part-time PhD student. Her research applies LLM-based methods to SoC verification and RTL debugging, informed by prior experience in IP-level verification.

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  Youshu Ji

  AI Engineer

  Youshu is an AI engineer, currently working on our project of LLM-based agile hardware design and verification. GitHub.

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  Yushu Du

  Hardware Engineer

  Yushu is a hardware engineer working on UVM-based verification for CPU designs. His current work focuses on UVM testbench development and functional verification of processor RTL.

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  Chuanwang Xiong

  AI Engineer

  Chuanwang is an AI engineer focusing on AI-driven methods for EDA. His current work explores the use of LLMs to support hardware design verification, with an emphasis on automating verification tasks and improving debugging efficiency.

Former group members continue their careers in academia and the semiconductor industry.

• Wei Tang · former Master's Student

  Now a CPU design engineer at Xiaomi. Wei worked on safety-critical RISC-V SoCs, microarchitectural RTL, and checker hardware between primary and redundant cores.

• Yiming Li · former Master's Student

  Now a design engineer at OmniVision Group. Yiming worked on safety-critical RISC-V processor microarchitecture, including redundant execution and error-detection mechanisms.

• Jing Wang · former Research Assistant

  Now a PhD researcher at Huazhong University of Science & Technology (HUST). Jing worked on prefetching and quantisation for NPUs.

• Yunpeng Zhu · former Master's Student

  Now an IC design engineer at BYD. Yunpeng researched instruction-analysis coprocessors (shadow stack, address sanitiser, etc.) and architectural support and hardware/software co-design for scalar processors.

• Hongtao Liu · former Master's Student

  Now an IC design engineer at Huawei. Hongtao worked on high-speed interconnects between CPU and accelerators, focusing on optimising data-transfer protocols and reducing communication latency in heterogeneous computing systems.