Zhe Jiang 江哲
I am a postdoctoral scholar in the Computer Architecture Group, at the Department of Computer Science and Technology, University of Cambridge, United Kingdom.
I am broadly interested in the architecture, micro-architecture, and design automation for emerging computing systems, with a particular focus on improving functional safety, security, reliability, and timing-predictability of automotive, cloud and embedded computing systems.
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I am currently a postdoctoral researcher in the Computer Architecture Group, at the Department of Computer Science and Technology, University of Cambridge, United Kingdom,
where I closely work with Timothy M. Jones and Sam Ainsworth to explore microarchitectural supports to improve the security of out-of-ordering superscalar processors.
Formally, I worked as a
design engineer (2020-2022) at the Department of Central Engineering, ARM, United Kingdom,
where I worked on the architecture and micro-architecture for server System-on-Chips (SoC)s. Our team have successfully delivered serval many-core (128/256-core) SoCs featured with Neoverse processors (ARM V9), e.g., Genesis (5nm) and Bravo (3nm), for Microsoft's and BytaDance's data centres.
safety architect (2018 - 2020) at the Functional Safety Competency Centre (FSCC), Renesas Electronics, United Kingdom,
where I worked on the architecture and safety architecture for automotive micro-controllers. Our team have successfully delivered serval ASIL-D micro-controllers for Bosch's and Denso's ECUs, including RH850/U216 (28nm) -- the World's First 28nm Cross-Domain MCU featuring virtualisation.
PhD. student (2014 - 2018) in the Real-Time Systems Group, at the Department of Computer Science, University of York, United Kingdom,
where I supervised by Neil Audsley to explore the architecture and micro-architecture for real-time Network-on-Chips and Inputs/Outputs (I/Os). [Thesis: Real-Time I/O System for Many-core Embedded Systems].
The capabilities of the computing systems have grown rapidly in the last decade, driven by the ground-breaking research explored in academia (e.g., machine learning) and the extensive validation performed in industry (e.g., simulations and real-world tests).
It is optimistically predicted that in the near future many emerging life-critical systems (e.g., self-driving vehicles health-check robots) will be deployed around us to to greatly improve our life quality.
However, before this vision can be realised, a crucial challenge lies in ensuring the reliable safety assurance of these computing systems. My research is deeply rooted in this promising direction. Over the past decade, I have collaborated with numerous researchers and engineers from both academia and industry to develop safety-critical hardware for next-generation computing systems. This includes everything from individual hardware elements (e.g., processors, interconnects, Input/Outputs (I/Os), etc.) to entire System-on-Chips (SoCs). I have adopted a highly practical approach to my research, focusing on the development of new architectures, hardware engineering methodologies, and tool support that facilitate automated safety and performance analysis of hardware design. This guides engineers in enhancing performance while ensuring safety and security. My work has been validated through real-time theory and extensive experimental evaluations in both laboratory and industrial settings. Furthermore, my research outputs have been successfully implemented in various industrial products. For a detailed research statement, please email me.