Zhe Jiang 江哲
Academic Faculty · School of Integrated Circuits, Southeast University · Nanjing, China
I lead a research group on processor architecture for dependable, high-performance computing. Parallel and heterogeneous execution improve CPU and NPU throughput but enlarge the state space requiring protection and verification. We develop microarchitectures that pair high-performance execution with independent observation, fault containment and recovery. Their architectural contracts guide LLM-aided RTL implementation and verification, allowing simulation and coverage evidence to refine both the implementation and the architecture. My research is informed by a decade at Cambridge, York, Arm and Renesas, including contributions to production automotive and data-centre silicon.
Recruiting Research positions available. The group is recruiting 2027 PhD students, 2027 Master's students (ideally starting from the final year of their undergraduate degree), and 2026 research assistants, postdoctoral fellows, and hardware/software engineers on the following projects:
- Dependable architectures for out-of-order CPUs, NPUs and SoCs
- Parallel and heterogeneous microarchitectures for performance and assurance
- LLM-aided RTL design and verification
Prospective applicants should email me with a CV and brief statement of research interests.
Please visit my friend Prof. Ran Wei — we collaborate, and apparently, so do our homepages.
Short biography
I am an academic faculty member researching dependable processor architecture and agile hardware development. My group combines parallel and heterogeneous microarchitecture with architecture-guided RTL implementation and verification. My appointments are summarised below:
- Academic Faculty Southeast University 2024–present School of Integrated Circuits, Southeast University, Nanjing, China. Leading research on dependable processor architecture, with emphasis on heterogeneous parallelism and architecture-guided RTL design and verification.
- Postdoctoral Scholar University of Cambridge 2021–2024 Computer Architecture Group, Department of Computer Science and Technology, University of Cambridge, United Kingdom. Worked with Timothy M. Jones and Sam Ainsworth on microarchitectural support for the security and reliability of out-of-order superscalar processors.
- Design Engineer Arm Ltd. 2020–2022 Department of Central Engineering, Arm, United Kingdom. Worked on the architecture and microarchitecture of server System-on-Chips (SoCs). Our team successfully delivered several many-core (128- and 256-core) SoCs based on Neoverse processors (Armv9), including Genesis (5 nm) and Bravo (3 nm) for Microsoft's and ByteDance's data centres.
- Safety Architect Renesas Electronics 2018–2020 Functional Safety Competency Centre (FSCC), Renesas Electronics, United Kingdom. Worked on the architecture and safety architecture of automotive micro-controllers. Our team successfully delivered several ASIL-D micro-controllers for Bosch's and Denso's ECUs, including RH850/U216 (28 nm) — the world's first 28 nm cross-domain MCU featuring virtualisation.
- PhD Student University of York 2014–2018 Real-Time Systems Group, Department of Computer Science, University of York, United Kingdom. Supervised by Neil Audsley on the architecture and microarchitecture of real-time Networks-on-Chip and input/output (I/O) sub-systems [Thesis: Real-Time I/O System for Many-core Embedded Systems].
Research vision
Modern processors obtain performance by executing many operations concurrently and speculatively. Their state is distributed across pipelines, memory hierarchies, accelerators and interconnects, making faults and security violations difficult to observe where they originate. Our research treats dependability as an architectural property: the execution model must specify both useful computation and the evidence required to detect, localise and recover from incorrect behaviour.
Architecture
Defines performance and dependability contracts
Microarchitecture
Produces runtime evidence through observation, isolation and recovery
LLM-aided design & verification
Produces implementation evidence from RTL, simulation and coverage
At run time, heterogeneous parallelism produces this evidence. Independent, privileged execution contexts accompany the primary computation and observe selected instructions, dataflows or accelerator stages without duplicating the entire processor. This principle supports fine-grained security analysis in out-of-order cores, privileged error detection in safety-critical processors and targeted protection in NPUs. The microarchitecture integrates observation, isolation and recovery with the pipeline and memory system, preserving throughput while bounding assurance cost.
The same evidence requirement extends to implementation. Architectural contracts become specifications, RTL properties and verification goals; compilers, simulators and coverage tools expose deviations from those contracts. LLM-based agents use this executable feedback for RTL generation, UVM construction and debugging. Verification results also identify weak interfaces and under-specified behaviour, returning measured constraints to the next architectural revision.