Zhe Jiang 江哲
Academic Faculty · School of Integrated Circuits, Southeast University · Nanjing, China
Building increasingly powerful computers we can depend on
How can we keep computing systems dependable as they become more parallel, more heterogeneous and harder to understand? I study how computer architecture can help us manage this growing complexity. My group connects parallel and heterogeneous architectures, dependable execution, and agile design and verification. We aim to turn architectural advances into useful performance, contain the effects of faults, and make complex designs practical to implement, check and revise. This includes LLM-assisted development guided by architectural knowledge and verification feedback.
Research
A new accelerator or more concurrent execution can increase capability while changing data movement, shared state and the assumptions made by software. Components that work in isolation must also be checked in combination. As designs evolve, changes introduce new interactions and can invalidate earlier checks. Our research asks how architectural structure can help performance scale while keeping protection and verification practical. We study processors, memory systems, accelerators and supporting system software, with the aim of making each generation more capable and its behaviour easier to understand, protect and improve.
Parallel and Heterogeneous Architectures
How can growing parallelism and heterogeneity deliver useful performance?
We investigate how computation and data movement should be organised across cores, memory systems and accelerators. We seek architectures that turn concurrency and specialisation into performance and efficiency, accounting for the coordination, communication and resource constraints that determine application benefit.
Dependable Execution
How can local faults be kept from becoming system failures?
We study error detection, containment, recovery and isolation during execution. The aim is to preserve required behaviour under specified faults and violations, with modest performance, energy and hardware costs. Protection requirements also guide how components interact and share state.
Agile Design and Verification
How can development and verification keep pace with architectural complexity?
We develop methods to explore, implement, check and revise complex designs. LLM-assisted generation and debugging work alongside performance modelling, simulation and verification. Architectural knowledge and tool feedback guide these activities, aiming to shorten iterations while retaining meaningful checks against explicit requirements.
Turn concurrency into useful performance
Detect, contain and recover
LLM assistance and tool feedback
Our research agenda connects these directions through feedback. Architectural choices shape performance, protection boundaries and what must be implemented and checked. Protection requirements influence those choices; implementation and verification results reveal assumptions that need revisiting. Development verification checks implementations against stated requirements, while runtime mechanisms address specified problems during operation. We aim to make advances practical to build, dependable in use, and easier to carry into the next generation.
Recruiting Research positions available. The group is recruiting 2027 PhD students, 2027 Master's students (ideally starting from the final year of their undergraduate degree), and 2026 research assistants, postdoctoral fellows, and hardware/software engineers on the following projects:
- Parallel and Heterogeneous Architectures
- Dependable Execution
- Agile Design and Verification, including LLM-assisted development
Prospective applicants should email me with a CV and brief statement of research interests.
Please visit my friend Prof. Ran Wei — we collaborate, and apparently, so do our homepages.
Short biography
I work on computer architecture and the methods used to keep increasingly complex systems dependable. My research connects performance, runtime protection, and design and verification. My appointments are summarised below:
- Academic Faculty Southeast University 2024–present School of Integrated Circuits, Southeast University, Nanjing, China. Leading research on parallel and heterogeneous architectures, dependable execution, and agile design and verification.
- Postdoctoral Scholar University of Cambridge 2021–2024 Computer Architecture Group, Department of Computer Science and Technology, University of Cambridge, United Kingdom. Worked with Timothy M. Jones and Sam Ainsworth on microarchitectural support for the security and reliability of out-of-order superscalar processors.
- Design Engineer Arm Ltd. 2020–2022 Department of Central Engineering, Arm, United Kingdom. Worked on the architecture and microarchitecture of server System-on-Chips (SoCs). Our team successfully delivered several many-core (128- and 256-core) SoCs based on Neoverse processors (Armv9), including Genesis (5 nm) and Bravo (3 nm) for Microsoft's and ByteDance's data centres.
- Safety Architect Renesas Electronics 2018–2020 Functional Safety Competency Centre (FSCC), Renesas Electronics, United Kingdom. Worked on the architecture and safety architecture of automotive micro-controllers. Our team successfully delivered several ASIL-D micro-controllers for Bosch's and Denso's ECUs, including RH850/U216 (28 nm) — the world's first 28 nm cross-domain MCU featuring virtualisation.
- PhD Student University of York 2014–2018 Real-Time Systems Group, Department of Computer Science, University of York, United Kingdom. Supervised by Neil Audsley on the architecture and microarchitecture of real-time Networks-on-Chip and input/output (I/O) sub-systems [Thesis: Real-Time I/O System for Many-core Embedded Systems].