Zhe Jiang 江哲
Academic Faculty · School of Integrated Circuits, Southeast University · Nanjing, China
I lead a research group working on the architecture, micro-architecture and design automation of next-generation computing systems, with a focus on improving their instruction- and memory-level parallelism, safety, reliability, security, and deployment efficiency. Drawing on a decade of experience across academia (Cambridge, York) and industry (Arm, Renesas), my work spans full-stack hardware design — from individual hardware elements (processors, interconnects, I/Os) to entire System-on-Chips — and has been adopted in production silicon shipping in automotive and data-centre products.
Recruiting We are hiring — multiple openings. Our group is recruiting 2027 PhD students, 2027 Master's students (ideally starting from the final year of their undergraduate degree), and 2026 research assistants, postdoctoral fellows, and hardware/software engineers on the following projects:
- LLM-aided hardware development
- (Micro-)architecture for safety-critical out-of-order processors
- (Micro-)architecture for lightweight LLM accelerators
Interested? Please email me with your CV and a short statement of interest.
Please also visit my friend Prof. Ran Wei's homepage — we collaborate closely, and even his homepage bears a striking resemblance to mine.
Short biography
I am an academic faculty member working on computer architecture, micro-architectural safety and security, timing-critical systems, and LLM-based design automation. My career to date:
- Academic Faculty Southeast University 2024–present School of Integrated Circuits, Southeast University, Nanjing, China. Leading a research group on the architecture and micro-architecture of safety- and security-critical processors, lightweight LLM accelerators, and LLM-aided hardware design automation.
- Postdoctoral Scholar University of Cambridge 2021–2024 Computer Architecture Group, Department of Computer Science and Technology, University of Cambridge, United Kingdom. Worked with Timothy M. Jones and Sam Ainsworth on micro-architectural support for the security and reliability of out-of-order superscalar processors.
- Design Engineer Arm Ltd. 2020–2022 Department of Central Engineering, Arm, United Kingdom. Worked on the architecture and micro-architecture of server System-on-Chips (SoCs). Our team successfully delivered several many-core (128- and 256-core) SoCs based on Neoverse processors (Armv9), including Genesis (5 nm) and Bravo (3 nm) for Microsoft's and ByteDance's data centres.
- Safety Architect Renesas Electronics 2018–2020 Functional Safety Competency Centre (FSCC), Renesas Electronics, United Kingdom. Worked on the architecture and safety architecture of automotive micro-controllers. Our team successfully delivered several ASIL-D micro-controllers for Bosch's and Denso's ECUs, including RH850/U216 (28 nm) — the world's first 28 nm cross-domain MCU featuring virtualisation.
- PhD Student University of York 2014–2018 Real-Time Systems Group, Department of Computer Science, University of York, United Kingdom. Supervised by Neil Audsley on the architecture and micro-architecture of real-time Networks-on-Chip and input/output (I/O) sub-systems [Thesis: Real-Time I/O System for Many-core Embedded Systems].
Research vision
The capabilities of computing systems have grown rapidly over the past decade, driven by ground-breaking research in academia (e.g., machine learning) and extensive validation in industry (e.g., simulations and real-world tests). It is optimistically predicted that, in the near future, many emerging life-critical systems — such as self-driving vehicles and health-care robots — will be deployed around us, greatly improving our quality of life.
Before this vision can be realised, however, a crucial challenge remains: ensuring the reliable safety assurance of these computing systems. My research is rooted in this direction. Over the past decade, I have collaborated with numerous researchers and engineers from both academia and industry to develop safety-critical hardware for next-generation computing systems — from individual hardware elements (processors, interconnects, I/Os, etc.) to entire System-on-Chips (SoCs). I take a highly practical approach, focusing on new architectures, hardware-engineering methodologies, and tool support that enable automated safety and performance analysis of hardware designs. This guides engineers in enhancing performance while ensuring safety and security. My work has been validated through real-time theory and through extensive experimental evaluation in both laboratory and industrial settings, and several outputs have been adopted in industrial products. For a detailed research statement, please email me.